The present invention relates to circuitry such as used in microelectronics.
The microelectronics industry has experienced an ever increasing demand for smaller and faster electronic devices able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture thin, low-cost, high-performance, low-power and high IO density integrated circuits (ICs), and interconnect similar or dissimilar ICs into a thin, reliable, low-cost, high-performance, and low-power package. These are conflicting goals since thinner ICs are harder to interconnect in a reliable, low-cost manner.
To address the packaging cost and reliability objectives, ICs and other circuits are often interconnected through intermediate substrates such as wiring substrates (e.g. printed circuit boards or other types) and interposers. FIG. 1 shows an exemplary package of multiple ICs 110 connected to each other and/or other circuits (not shown) through interposers (“ITP”) 120.1 and 120.2 and wiring substrate 130. ICs 110 are attached to the interposers in a flip-chip manner, i.e. the ICs' bottom contact pads 110C are attached to top contact pads 120C.T of respective interposers 120.1, 120.2 by connections 134. Connections 134 can be formed by solder or solder composite, adhesive, diffusion bonding, or some other means. Interposers 120 (i.e. 120.1 and 120.2) have bottom contact pads 120C.B attached to the wiring substrate's top contact pads 130C by connections 138 (e.g. solder). Each interposer 120 (i.e. 120.1 and 120.2) includes conductive lines 120L interconnecting its contact pads 120C.T and 120C.B in a desired pattern in order to connect the respective ICs 110 to each other and to wiring substrate 130. Wiring substrate 130 has conductive lines 130L interconnecting the wiring substrate's contact pads 130C and hence interconnecting the ICs 110 located on the same or different interposers 120.
For cost reduction purposes, wiring substrates 130 are made of inexpensive, possibly non-semiconductor material (e.g. organic or ceramic) processed by inexpensive techniques (e.g. printing) to form the conductive lines 130L. In contrast, ICs 110 are manufactured by high precision but more expensive semiconductor technology allowing the ICs to be small and have high performance. As a result, the ICs' contact pads 110C can be spaced closer to each other (at a lower pitch) than the wiring substrate's contact pads 130C. Consequently, the ICs cannot be flip-chip attached to the wiring substrate. Interposers 120 “redistribute” the contact pads: the interposers 120 can be manufactured by high precision technology, with the top contact pads 120C.T matching the ICs' contact pads 110C but with the bottom contact pads 120C.B matching the wiring substrate.
Further, interposers 120 absorb and dissipate some of the heat generated by the ICs and thus reduce thermo-mechanical stresses (mechanical stresses resulting from thermal expansion). Also, if the interposers' coefficients of thermal expansion (CTE) are intermediate between the wiring substrate and the ICs, or are close to the ICs, then the IC-to-interposer connections 134 experience less thermo-mechanical stress. The connections 138 between the interposers and the wiring substrate may experience higher stresses due to the CTE mismatch between the interposers and the wiring substrate, but connections 138 can be made larger due to their high pitch, and therefore can be sturdy and reliable.
Each IC or interposer is typically manufactured in a large wafer format with other ICs or interposers, and the wafer is diced (singulated) into individual ICs or interposers (which are called die or chips). The ICs 110, interposers 120, and wiring substrate 130 can be attached to each other after dicing; see e.g. U.S. Pat. No. 8,138,015 B2 issued Mar. 20, 2012 to Joseph et al. However, reliable attachment of tiny, fragile ICs 110 to interposers is difficult. Therefore, wafer-level packaging is used, with some of the ICs or interposers being attached to each other before singulation and possibly even before the end of wafer processing; for instance, ICs 110 can be attached to interposers 120 before singulation of at least some of wafers. Moreover, some of the wafers can be initially thick for increased reliability, and can be thinned late in the manufacturing process; in such cases, some of the IC and interposer attachments can be performed before wafer thinning.
One example is shown in FIG. 2A: the interposer wafer 120W has not yet been singulated, but will be singulated along the lines 140 to form multiple interposers of the type of interposer 120.1 of FIG. 1. The IC wafers have been singulated, and ICs 110 have been attached to interposer wafer 120W. Moreover, in FIG. 2A, the interposers' bottom contact pads 120C.B have not yet been formed, and the interposer wafer 120W is thicker (and hence stronger) than its final size; the ICs have been attached before thinning of wafer 120W. Interposers 120.2 are fabricated in another wafer (not shown), possibly using the same or different wafer-level packaging techniques.
The interposer wafer of FIG. 2A is based on a substrate 120S (e.g. silicon or glass or other material with a CTE similar to the ICs). The interposer's conductive lines 120L include vertical vias 120LV going down into substrate 120S, and include other lines 120LH at the top of the wafer. Lines 120LH are electrically insulated from each other and from substrate 120S by dielectric 210D; lines 120LH and dielectric 210D form a “redistribution layer” (RDL) 210 used to redistribute the contact pads as described above.
Interposer wafer 120W is thinned from the bottom to expose the bottom ends of vias 120LV; the bottom ends will be used as contact pads 120C.B. However, in the wafer thinning operation, wafer 120W and substrate 120S become thin and fragile, easy to damage during or after thinning. Also, thinned wafer 120W can be warped, which complicates further processing including interposer attachment to wiring substrate 130. Therefore, before thinning, wafer 120W with ICs 110 attached at the top, can be strengthened by mold compound 310 (FIG. 2B) and carrier 320. Mold compound 310 is typically an organic polymeric material with fillers (e.g. silica). Carrier 320 can be a glass or silicon wafer, attached by adhesive 330.
As shown in FIG. 3, interposer substrate 120S is then thinned from the bottom, e.g. by mechanical and/or chemical processes, to expose the vias 120LV. The bottom ends of vias 120LV become contact pads 120C.B. Additional metal (e.g. solder) can be deposited on these bottom ends if needed. Then carrier 320 is debonded or ground away, the interposer wafer is singulated along lines 140 together with mold 310, and individual interposers 120.1, with ICs 110C on top, are attached to the same or different wiring substrates 130 as in FIG. 1.
Regrettably, mold compounds contribute to warpage because their CTEs are typically higher than for interposer wafers. The warpage progressively increases as the interposer wafer is thinned with mold compound on top. This complicates the process required to uniformly expose the vias 120LV during thinning. The increased warpage also complicates attaching the singulated substrate 120S to the wiring substrates 130.
U.S. pre-grant patent publication no. 2013/0082399 (Apr. 4, 2013; Kim et al.) describes a “semiconductor package including an internal package” with “at least one semiconductor chip sealed with an internal seal” (Abstract). The internal package is mounted on “an internal substrate”, and sealed by “an external seal” (Id.). The Young's modulus of the internal seal is smaller than of the external seal to reduce warpage (Id.). Both seals can be made of filled resin, but the external seal has more filler to increase its Young's modulus (paragraphs 0056-0057, 0064-0065).
Alternative packaging techniques are desirable.